495 lines
17 KiB
C
495 lines
17 KiB
C
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/* libFLAC - Free Lossless Audio Codec library
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* Copyright (C) 2001-2009 Josh Coalson
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* Copyright (C) 2011-2014 Xiph.Org Foundation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* - Neither the name of the Xiph.org Foundation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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# include <config.h>
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#endif
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#include "include/private/cpu.h"
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#if 0
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#include <stdlib.h>
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#include <memory.h>
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#include <stdio.h>
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#endif
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#if defined FLAC__CPU_IA32
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# include <signal.h>
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static void disable_sse(FLAC__CPUInfo *info)
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{
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info->ia32.sse = false;
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info->ia32.sse2 = false;
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info->ia32.sse3 = false;
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info->ia32.ssse3 = false;
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info->ia32.sse41 = false;
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info->ia32.sse42 = false;
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}
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static void disable_avx(FLAC__CPUInfo *info)
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{
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info->ia32.avx = false;
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info->ia32.avx2 = false;
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info->ia32.fma = false;
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}
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#elif defined FLAC__CPU_X86_64
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static void disable_avx(FLAC__CPUInfo *info)
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{
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info->x86.avx = false;
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info->x86.avx2 = false;
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info->x86.fma = false;
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}
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#endif
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#if defined (__NetBSD__) || defined(__OpenBSD__)
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <machine/cpu.h>
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#endif
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
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#include <sys/types.h>
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#include <sys/sysctl.h>
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#endif
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#if defined(__APPLE__)
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/* how to get sysctlbyname()? */
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#endif
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#ifdef FLAC__CPU_IA32
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/* these are flags in EDX of CPUID AX=00000001 */
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static const unsigned FLAC__CPUINFO_IA32_CPUID_CMOV = 0x00008000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_MMX = 0x00800000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_FXSR = 0x01000000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSE = 0x02000000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSE2 = 0x04000000;
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#endif
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/* these are flags in ECX of CPUID AX=00000001 */
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSE3 = 0x00000001;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSSE3 = 0x00000200;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSE41 = 0x00080000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_SSE42 = 0x00100000;
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#if defined FLAC__AVX_SUPPORTED
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/* these are flags in ECX of CPUID AX=00000001 */
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static const unsigned FLAC__CPUINFO_IA32_CPUID_OSXSAVE = 0x08000000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_AVX = 0x10000000;
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static const unsigned FLAC__CPUINFO_IA32_CPUID_FMA = 0x00001000;
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/* these are flags in EBX of CPUID AX=00000007 */
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static const unsigned FLAC__CPUINFO_IA32_CPUID_AVX2 = 0x00000020;
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#endif
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/*
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* Extra stuff needed for detection of OS support for SSE on IA-32
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*/
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#if defined(FLAC__CPU_IA32) && !defined FLAC__NO_ASM && (defined FLAC__HAS_NASM || defined FLAC__HAS_X86INTRIN) && !defined FLAC__NO_SSE_OS && !defined FLAC__SSE_OS
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# if defined(__linux__)
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/*
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* If the OS doesn't support SSE, we will get here with a SIGILL. We
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* modify the return address to jump over the offending SSE instruction
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* and also the operation following it that indicates the instruction
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* executed successfully. In this way we use no global variables and
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* stay thread-safe.
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*
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* 3 + 3 + 6:
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* 3 bytes for "xorps xmm0,xmm0"
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* 3 bytes for estimate of how long the follwing "inc var" instruction is
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* 6 bytes extra in case our estimate is wrong
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* 12 bytes puts us in the NOP "landing zone"
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*/
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# include <sys/ucontext.h>
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static void sigill_handler_sse_os(int signal, siginfo_t *si, void *uc)
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{
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(void)signal, (void)si;
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((ucontext_t*)uc)->uc_mcontext.gregs[14/*REG_EIP*/] += 3 + 3 + 6;
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}
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# elif defined(_MSC_VER)
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# include <windows.h>
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# endif
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#endif
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void FLAC__cpu_info(FLAC__CPUInfo *info)
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{
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/*
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* IA32-specific
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*/
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#ifdef FLAC__CPU_IA32
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FLAC__bool ia32_fxsr = false;
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FLAC__bool ia32_osxsave = false;
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(void) ia32_fxsr; (void) ia32_osxsave; /* to avoid warnings about unused variables */
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memset(info, 0, sizeof(*info));
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info->type = FLAC__CPUINFO_TYPE_IA32;
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#if !defined FLAC__NO_ASM && (defined FLAC__HAS_NASM || defined FLAC__HAS_X86INTRIN)
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info->use_asm = true; /* we assume a minimum of 80386 with FLAC__CPU_IA32 */
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#ifdef FLAC__HAS_X86INTRIN
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if(!FLAC__cpu_have_cpuid_x86())
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return;
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#else
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if(!FLAC__cpu_have_cpuid_asm_ia32())
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return;
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#endif
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{
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/* http://www.sandpile.org/x86/cpuid.htm */
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#ifdef FLAC__HAS_X86INTRIN
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FLAC__uint32 flags_eax, flags_ebx, flags_ecx, flags_edx;
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FLAC__cpu_info_x86(1, &flags_eax, &flags_ebx, &flags_ecx, &flags_edx);
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#else
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FLAC__uint32 flags_ecx, flags_edx;
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FLAC__cpu_info_asm_ia32(&flags_edx, &flags_ecx);
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#endif
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info->ia32.cmov = (flags_edx & FLAC__CPUINFO_IA32_CPUID_CMOV )? true : false;
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info->ia32.mmx = (flags_edx & FLAC__CPUINFO_IA32_CPUID_MMX )? true : false;
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ia32_fxsr = (flags_edx & FLAC__CPUINFO_IA32_CPUID_FXSR )? true : false;
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info->ia32.sse = (flags_edx & FLAC__CPUINFO_IA32_CPUID_SSE )? true : false;
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info->ia32.sse2 = (flags_edx & FLAC__CPUINFO_IA32_CPUID_SSE2 )? true : false;
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info->ia32.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 )? true : false;
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info->ia32.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false;
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info->ia32.sse41 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE41)? true : false;
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info->ia32.sse42 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE42)? true : false;
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#if defined FLAC__HAS_X86INTRIN && defined FLAC__AVX_SUPPORTED
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ia32_osxsave = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_OSXSAVE)? true : false;
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info->ia32.avx = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_AVX )? true : false;
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info->ia32.fma = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_FMA )? true : false;
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FLAC__cpu_info_x86(7, &flags_eax, &flags_ebx, &flags_ecx, &flags_edx);
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info->ia32.avx2 = (flags_ebx & FLAC__CPUINFO_IA32_CPUID_AVX2 )? true : false;
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#endif
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}
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#ifdef DEBUG
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fprintf(stderr, "CPU info (IA-32):\n");
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fprintf(stderr, " CMOV ....... %c\n", info->ia32.cmov ? 'Y' : 'n');
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fprintf(stderr, " MMX ........ %c\n", info->ia32.mmx ? 'Y' : 'n');
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fprintf(stderr, " SSE ........ %c\n", info->ia32.sse ? 'Y' : 'n');
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fprintf(stderr, " SSE2 ....... %c\n", info->ia32.sse2 ? 'Y' : 'n');
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fprintf(stderr, " SSE3 ....... %c\n", info->ia32.sse3 ? 'Y' : 'n');
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fprintf(stderr, " SSSE3 ...... %c\n", info->ia32.ssse3 ? 'Y' : 'n');
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fprintf(stderr, " SSE41 ...... %c\n", info->ia32.sse41 ? 'Y' : 'n');
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fprintf(stderr, " SSE42 ...... %c\n", info->ia32.sse42 ? 'Y' : 'n');
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# if defined FLAC__HAS_X86INTRIN && defined FLAC__AVX_SUPPORTED
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fprintf(stderr, " AVX ........ %c\n", info->ia32.avx ? 'Y' : 'n');
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fprintf(stderr, " FMA ........ %c\n", info->ia32.fma ? 'Y' : 'n');
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fprintf(stderr, " AVX2 ....... %c\n", info->ia32.avx2 ? 'Y' : 'n');
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# endif
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#endif
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/*
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* now have to check for OS support of SSE instructions
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*/
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if(info->ia32.sse) {
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#if defined FLAC__NO_SSE_OS
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/* assume user knows better than us; turn it off */
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disable_sse(info);
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#elif defined FLAC__SSE_OS
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/* assume user knows better than us; leave as detected above */
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
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int sse = 0;
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size_t len;
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/* at least one of these must work: */
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.instruction_sse", &sse, &len, NULL, 0) == 0 && sse);
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.optional.sse" , &sse, &len, NULL, 0) == 0 && sse); /* __APPLE__ ? */
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if(!sse)
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disable_sse(info);
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#elif defined(__NetBSD__) || defined (__OpenBSD__)
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# if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
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int val = 0, mib[2] = { CTL_MACHDEP, CPU_SSE };
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size_t len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val)
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disable_sse(info);
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else { /* double-check SSE2 */
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mib[1] = CPU_SSE2;
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len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val) {
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disable_sse(info);
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info->ia32.sse = true;
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}
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}
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# else
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disable_sse(info);
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# endif
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#elif defined(__linux__)
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int sse = 0;
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struct sigaction sigill_save;
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struct sigaction sigill_sse;
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sigill_sse.sa_sigaction = sigill_handler_sse_os;
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#ifdef __ANDROID__
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sigemptyset (&sigill_sse.sa_mask);
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#else
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__sigemptyset(&sigill_sse.sa_mask);
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#endif
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sigill_sse.sa_flags = SA_SIGINFO | SA_RESETHAND; /* SA_RESETHAND just in case our SIGILL return jump breaks, so we don't get stuck in a loop */
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if(0 == sigaction(SIGILL, &sigill_sse, &sigill_save))
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{
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/* http://www.ibiblio.org/gferg/ldp/GCC-Inline-Assembly-HOWTO.html */
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/* see sigill_handler_sse_os() for an explanation of the following: */
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asm volatile (
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"xorps %%xmm0,%%xmm0\n\t" /* will cause SIGILL if unsupported by OS */
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"incl %0\n\t" /* SIGILL handler will jump over this */
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/* landing zone */
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"nop\n\t" /* SIGILL jump lands here if "inc" is 9 bytes */
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t" /* SIGILL jump lands here if "inc" is 3 bytes (expected) */
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"nop\n\t"
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"nop" /* SIGILL jump lands here if "inc" is 1 byte */
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: "=r"(sse)
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: "0"(sse)
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);
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sigaction(SIGILL, &sigill_save, NULL);
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}
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if(!sse)
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disable_sse(info);
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#elif defined(_MSC_VER)
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__try {
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__asm {
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xorps xmm0,xmm0
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER) {
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if (_exception_code() == STATUS_ILLEGAL_INSTRUCTION)
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disable_sse(info);
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}
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#elif defined(__GNUC__) /* MinGW goes here */
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int sse = 0;
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/* Based on the idea described in Agner Fog's manual "Optimizing subroutines in assembly language" */
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/* In theory, not guaranteed to detect lack of OS SSE support on some future Intel CPUs, but in practice works (see the aforementioned manual) */
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if (ia32_fxsr) {
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struct {
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FLAC__uint32 buff[128];
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} __attribute__((aligned(16))) fxsr;
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FLAC__uint32 old_val, new_val;
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asm volatile ("fxsave %0" : "=m" (fxsr) : "m" (fxsr));
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old_val = fxsr.buff[50];
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fxsr.buff[50] ^= 0x0013c0de; /* change value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* try to change SSE register */
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fxsr.buff[50] = old_val; /* restore old value in the buffer */
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asm volatile ("fxsave %0 " : "=m" (fxsr) : "m" (fxsr)); /* old value will be overwritten if SSE register was changed */
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new_val = fxsr.buff[50]; /* == old_val if FXRSTOR didn't change SSE register and (old_val ^ 0x0013c0de) otherwise */
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fxsr.buff[50] = old_val; /* again restore old value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* restore old values of registers */
|
||
|
|
|
||
|
|
if ((old_val^new_val) == 0x0013c0de)
|
||
|
|
sse = 1;
|
||
|
|
}
|
||
|
|
if(!sse)
|
||
|
|
disable_sse(info);
|
||
|
|
#else
|
||
|
|
/* no way to test, disable to be safe */
|
||
|
|
disable_sse(info);
|
||
|
|
#endif
|
||
|
|
#ifdef DEBUG
|
||
|
|
fprintf(stderr, " SSE OS sup . %c\n", info->ia32.sse ? 'Y' : 'n');
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else /* info->ia32.sse == false */
|
||
|
|
disable_sse(info);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* now have to check for OS support of AVX instructions
|
||
|
|
*/
|
||
|
|
if(info->ia32.avx && ia32_osxsave) {
|
||
|
|
FLAC__uint32 ecr = FLAC__cpu_xgetbv_x86();
|
||
|
|
if ((ecr & 0x6) != 0x6)
|
||
|
|
disable_avx(info);
|
||
|
|
#ifdef DEBUG
|
||
|
|
fprintf(stderr, " AVX OS sup . %c\n", info->ia32.avx ? 'Y' : 'n');
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else /* no OS AVX support*/
|
||
|
|
disable_avx(info);
|
||
|
|
#else
|
||
|
|
info->use_asm = false;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* x86-64-specific
|
||
|
|
*/
|
||
|
|
#elif defined FLAC__CPU_X86_64
|
||
|
|
FLAC__bool x86_osxsave = false;
|
||
|
|
(void) x86_osxsave; /* to avoid warnings about unused variables */
|
||
|
|
memset(info, 0, sizeof(*info));
|
||
|
|
info->type = FLAC__CPUINFO_TYPE_X86_64;
|
||
|
|
#if !defined FLAC__NO_ASM && defined FLAC__HAS_X86INTRIN
|
||
|
|
info->use_asm = true;
|
||
|
|
{
|
||
|
|
/* http://www.sandpile.org/x86/cpuid.htm */
|
||
|
|
FLAC__uint32 flags_eax, flags_ebx, flags_ecx, flags_edx;
|
||
|
|
FLAC__cpu_info_x86(1, &flags_eax, &flags_ebx, &flags_ecx, &flags_edx);
|
||
|
|
info->x86.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 )? true : false;
|
||
|
|
info->x86.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false;
|
||
|
|
info->x86.sse41 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE41)? true : false;
|
||
|
|
info->x86.sse42 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE42)? true : false;
|
||
|
|
#if defined FLAC__AVX_SUPPORTED
|
||
|
|
x86_osxsave = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_OSXSAVE)? true : false;
|
||
|
|
info->x86.avx = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_AVX )? true : false;
|
||
|
|
info->x86.fma = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_FMA )? true : false;
|
||
|
|
FLAC__cpu_info_x86(7, &flags_eax, &flags_ebx, &flags_ecx, &flags_edx);
|
||
|
|
info->x86.avx2 = (flags_ebx & FLAC__CPUINFO_IA32_CPUID_AVX2 )? true : false;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#ifdef DEBUG
|
||
|
|
fprintf(stderr, "CPU info (x86-64):\n");
|
||
|
|
fprintf(stderr, " SSE3 ....... %c\n", info->x86.sse3 ? 'Y' : 'n');
|
||
|
|
fprintf(stderr, " SSSE3 ...... %c\n", info->x86.ssse3 ? 'Y' : 'n');
|
||
|
|
fprintf(stderr, " SSE41 ...... %c\n", info->x86.sse41 ? 'Y' : 'n');
|
||
|
|
fprintf(stderr, " SSE42 ...... %c\n", info->x86.sse42 ? 'Y' : 'n');
|
||
|
|
# if defined FLAC__AVX_SUPPORTED
|
||
|
|
fprintf(stderr, " AVX ........ %c\n", info->x86.avx ? 'Y' : 'n');
|
||
|
|
fprintf(stderr, " FMA ........ %c\n", info->x86.fma ? 'Y' : 'n');
|
||
|
|
fprintf(stderr, " AVX2 ....... %c\n", info->x86.avx2 ? 'Y' : 'n');
|
||
|
|
# endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* now have to check for OS support of AVX instructions
|
||
|
|
*/
|
||
|
|
if(info->x86.avx && x86_osxsave) {
|
||
|
|
FLAC__uint32 ecr = FLAC__cpu_xgetbv_x86();
|
||
|
|
if ((ecr & 0x6) != 0x6)
|
||
|
|
disable_avx(info);
|
||
|
|
#ifdef DEBUG
|
||
|
|
fprintf(stderr, " AVX OS sup . %c\n", info->x86.avx ? 'Y' : 'n');
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else /* no OS AVX support*/
|
||
|
|
disable_avx(info);
|
||
|
|
#else
|
||
|
|
info->use_asm = false;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* unknown CPU
|
||
|
|
*/
|
||
|
|
#else
|
||
|
|
info->type = FLAC__CPUINFO_TYPE_UNKNOWN;
|
||
|
|
info->use_asm = false;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#if (defined FLAC__CPU_IA32 || defined FLAC__CPU_X86_64) && defined FLAC__HAS_X86INTRIN
|
||
|
|
|
||
|
|
#if defined _MSC_VER
|
||
|
|
#include <intrin.h> /* for __cpuid() and _xgetbv() */
|
||
|
|
#elif defined __GNUC__ && defined HAVE_CPUID_H
|
||
|
|
#include <cpuid.h> /* for __get_cpuid() and __get_cpuid_max() */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
FLAC__uint32 FLAC__cpu_have_cpuid_x86(void)
|
||
|
|
{
|
||
|
|
#ifdef FLAC__CPU_X86_64
|
||
|
|
return 1;
|
||
|
|
#else
|
||
|
|
# if defined _MSC_VER || defined __INTEL_COMPILER /* Do they support CPUs w/o CPUID support (or OSes that work on those CPUs)? */
|
||
|
|
FLAC__uint32 flags1, flags2;
|
||
|
|
__asm {
|
||
|
|
pushfd
|
||
|
|
pushfd
|
||
|
|
pop eax
|
||
|
|
mov flags1, eax
|
||
|
|
xor eax, 0x200000
|
||
|
|
push eax
|
||
|
|
popfd
|
||
|
|
pushfd
|
||
|
|
pop eax
|
||
|
|
mov flags2, eax
|
||
|
|
popfd
|
||
|
|
}
|
||
|
|
if (((flags1^flags2) & 0x200000) != 0)
|
||
|
|
return 1;
|
||
|
|
else
|
||
|
|
return 0;
|
||
|
|
# elif defined __GNUC__ && defined HAVE_CPUID_H
|
||
|
|
if (__get_cpuid_max(0, 0) != 0)
|
||
|
|
return 1;
|
||
|
|
else
|
||
|
|
return 0;
|
||
|
|
# else
|
||
|
|
return 0;
|
||
|
|
# endif
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void FLAC__cpu_info_x86(FLAC__uint32 level, FLAC__uint32 *eax, FLAC__uint32 *ebx, FLAC__uint32 *ecx, FLAC__uint32 *edx)
|
||
|
|
{
|
||
|
|
(void) level;
|
||
|
|
|
||
|
|
#if defined _MSC_VER || defined __INTEL_COMPILER
|
||
|
|
int cpuinfo[4];
|
||
|
|
int ext = level & 0x80000000;
|
||
|
|
__cpuid(cpuinfo, ext);
|
||
|
|
if((unsigned)cpuinfo[0] < level) {
|
||
|
|
*eax = *ebx = *ecx = *edx = 0;
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
#if defined FLAC__AVX_SUPPORTED
|
||
|
|
__cpuidex(cpuinfo, level, 0); /* for AVX2 detection */
|
||
|
|
#else
|
||
|
|
__cpuid(cpuinfo, level); /* some old compilers don't support __cpuidex */
|
||
|
|
#endif
|
||
|
|
*eax = cpuinfo[0]; *ebx = cpuinfo[1]; *ecx = cpuinfo[2]; *edx = cpuinfo[3];
|
||
|
|
#elif defined __GNUC__ && defined HAVE_CPUID_H
|
||
|
|
FLAC__uint32 ext = level & 0x80000000;
|
||
|
|
__cpuid(ext, *eax, *ebx, *ecx, *edx);
|
||
|
|
if (*eax < level) {
|
||
|
|
*eax = *ebx = *ecx = *edx = 0;
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
__cpuid_count(level, 0, *eax, *ebx, *ecx, *edx);
|
||
|
|
#else
|
||
|
|
*eax = *ebx = *ecx = *edx = 0;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
FLAC__uint32 FLAC__cpu_xgetbv_x86(void)
|
||
|
|
{
|
||
|
|
#if (defined _MSC_VER || defined __INTEL_COMPILER) && defined FLAC__AVX_SUPPORTED
|
||
|
|
return (FLAC__uint32)_xgetbv(0);
|
||
|
|
#elif defined __GNUC__
|
||
|
|
FLAC__uint32 lo, hi;
|
||
|
|
asm volatile (".byte 0x0f, 0x01, 0xd0" : "=a"(lo), "=d"(hi) : "c" (0));
|
||
|
|
return lo;
|
||
|
|
#else
|
||
|
|
return 0;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* (FLAC__CPU_IA32 || FLAC__CPU_X86_64) && FLAC__HAS_X86INTRIN */
|