63 lines
2.9 KiB
Properties
63 lines
2.9 KiB
Properties
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lexer.*.vh=verilog
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keywords.*.vh= \
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always and assign automatic \
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begin buf bufif0 bufif1 \
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case casex casez cell cmos config \
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deassign default defparam design disable \
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edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
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for force forever fork function \
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generate genvar \
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highz0 highz1 \
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if ifnone incdir include initial inout input instance integer \
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join \
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large liblist library localparam \
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macromodule medium module \
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nand negedge nmos nor noshowcancelled not notif0 notif1 \
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or output \
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parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
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rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
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scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
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table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
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unsigned use uwire \
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vectored \
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wait wand weak0 weak1 while wire wor \
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xnor xor
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keywords2.*.vh=special
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keywords3.*.vh= \
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$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
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$bitstoreal \
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$countdrivers \
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$display $displayb $displayh $displayo \
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$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
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$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
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$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $feof $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
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$getpattern \
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$history $hold \
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$incsave $input $itor \
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$key \
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$list $log \
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$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
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$nochange $nokey $nolog \
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$period $printtimescale \
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$q_add $q_exam $q_full $q_initialize $q_remove \
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$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
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$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
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$test$plusargs $time $timeformat $timeskew \
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$ungetc $unsigned \
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$value$plusargs \
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$width $writeb $writeh $write $writeo
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keywords4.*.vh=my_var
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keywords5.*.vh=synopsys parallel_case infer_mux TODO
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fold=1
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fold.compact=0
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fold.comment=1
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fold.preprocessor=1
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fold.at.else=1
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fold.verilog.flags=1 # fold module definitions
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lexer.verilog.track.preprocessor=1
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lexer.verilog.update.preprocessor=1
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lexer.verilog.portstyling=1
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lexer.verilog.fold.preprocessor.else=1
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