fix build under newer KConfig by bump cmake min version
This commit is contained in:
97
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh
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97
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh
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// Examples drawn from https://verilogams.com/refman/basics/index.html
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// SCE_V_DEFAULT {0}
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/*
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* SCE_V_COMMENT {1}
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*/
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// SCE_V_COMMENTLINE {2}
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// multiple
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// comment lines
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// are folded
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//{ explicit folds
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// are folded,
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//} too
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//! SCE_V_COMMENTLINEBANG {3}
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//! multiple
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//! bang comments
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//! are folded
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// SCE_V_NUMBER {4}
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1'b0
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8'hx
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8'hfffx
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12'hfx
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64'o0
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0x7f
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0o23
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0b1011
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42_839
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0.1
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1.3u
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5.46K
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1.2E12
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1.30e-2
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236.123_763e-12
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// SCE_V_WORD {5}
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always
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// SCE_V_STRING {6}
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"\tsome\ttext\r\n"
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// SCE_V_WORD2 {7}
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special
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// SCE_V_WORD3 {8}
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$async$and$array
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// SCE_V_PREPROCESSOR {9}
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`define __VAMS_ENABLE__
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`ifdef __VAMS_ENABLE__
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parameter integer del = 1 from [1:100];
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`else
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parameter del = 1;
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`endif
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// SCE_V_OPERATOR {10}
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+-/=!@#%^&*()[]{}<|>~
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// SCE_V_IDENTIFIER {11}
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q
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x$z
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\my_var
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\/x1/n1
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\\x1\n1
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\{a,b}
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\V(p,n)
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// SCE_V_STRINGEOL {12}
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"\n
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// SCE_V_USER {19}
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my_var
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// SCE_V_COMMENT_WORD {20}
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// TODO write a comment
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module mod(clk, q, reset) // folded when fold.verilog.flags=1
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// SCE_V_INPUT {21}
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input clk;
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// SCE_V_OUTPUT {22}
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output q;
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// SCE_V_INOUT {23}
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inout reset;
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endmodule
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// SCE_V_PORT_CONNECT {24}
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mod m1(
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.clk(clk),
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.q(q),
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.reset(reset)
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);
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98
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh.folded
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98
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh.folded
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0 400 400 // Examples drawn from https://verilogams.com/refman/basics/index.html
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0 400 400
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0 400 400 // SCE_V_DEFAULT {0}
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0 400 400
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2 400 401 + /*
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0 401 401 | * SCE_V_COMMENT {1}
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0 401 400 | */
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0 400 400
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2 400 401 + // SCE_V_COMMENTLINE {2}
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0 401 401 | // multiple
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0 401 401 | // comment lines
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0 401 400 | // are folded
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0 400 400
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2 400 402 + //{ explicit folds
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0 402 402 | // are folded,
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0 402 400 | //} too
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0 400 400
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2 400 401 + //! SCE_V_COMMENTLINEBANG {3}
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0 401 401 | //! multiple
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0 401 401 | //! bang comments
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0 401 400 | //! are folded
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0 400 400
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0 400 400 // SCE_V_NUMBER {4}
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0 400 400 1'b0
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0 400 400 8'hx
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0 400 400 8'hfffx
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0 400 400 12'hfx
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0 400 400 64'o0
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0 400 400 0x7f
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0 400 400 0o23
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0 400 400 0b1011
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0 400 400 42_839
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0 400 400 0.1
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0 400 400 1.3u
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0 400 400 5.46K
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0 400 400 1.2E12
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0 400 400 1.30e-2
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0 400 400 236.123_763e-12
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0 400 400
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0 400 400 // SCE_V_WORD {5}
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0 400 400 always
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0 400 400
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0 400 400 // SCE_V_STRING {6}
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0 400 400 "\tsome\ttext\r\n"
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0 400 400
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0 400 400 // SCE_V_WORD2 {7}
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0 400 400 special
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0 400 400
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0 400 400 // SCE_V_WORD3 {8}
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0 400 400 $async$and$array
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0 400 400
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0 400 400 // SCE_V_PREPROCESSOR {9}
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0 400 400 `define __VAMS_ENABLE__
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2 400 401 + `ifdef __VAMS_ENABLE__
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0 401 401 | parameter integer del = 1 from [1:100];
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2 400 401 + `else
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0 401 401 | parameter del = 1;
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0 401 400 | `endif
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0 400 400
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0 400 400 // SCE_V_OPERATOR {10}
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0 400 400 +-/=!@#%^&*()[]{}<|>~
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0 400 400
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0 400 400 // SCE_V_IDENTIFIER {11}
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0 400 400 q
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0 400 400 x$z
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0 400 400 \my_var
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0 400 400 \/x1/n1
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0 400 400 \\x1\n1
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0 400 400 \{a,b}
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0 400 400 \V(p,n)
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0 400 400
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0 400 400 // SCE_V_STRINGEOL {12}
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0 400 400 "\n
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0 400 400
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0 400 400 // SCE_V_USER {19}
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0 400 400 my_var
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0 400 400
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2 400 401 + // SCE_V_COMMENT_WORD {20}
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0 401 400 | // TODO write a comment
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0 400 400
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2 400 401 + module mod(clk, q, reset) // folded when fold.verilog.flags=1
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0 401 401 | // SCE_V_INPUT {21}
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0 401 401 | input clk;
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0 401 401 |
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0 401 401 | // SCE_V_OUTPUT {22}
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0 401 401 | output q;
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0 401 401 |
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0 401 401 | // SCE_V_INOUT {23}
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0 401 401 | inout reset;
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0 401 400 | endmodule
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0 400 400
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0 400 400 // SCE_V_PORT_CONNECT {24}
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2 400 401 + mod m1(
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0 401 401 | .clk(clk),
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0 401 401 | .q(q),
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0 401 401 | .reset(reset)
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0 401 400 | );
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0 400 0
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97
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh.styled
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97
3rdparty/lexilla540/lexilla/test/examples/verilog/AllStyles.vh.styled
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{2}// Examples drawn from https://verilogams.com/refman/basics/index.html
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{0}
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{2}// SCE_V_DEFAULT {0}
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{0}
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{1}/*
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* SCE_V_COMMENT {1}
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*/{0}
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{2}// SCE_V_COMMENTLINE {2}
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// multiple
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// comment lines
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// are folded
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{0}
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{2}//{ explicit folds
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// are folded,
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//} too
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{0}
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{3}//! SCE_V_COMMENTLINEBANG {3}
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//! multiple
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//! bang comments
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//! are folded
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{0}
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{2}// SCE_V_NUMBER {4}
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{4}1'b0{0}
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{4}8'hx{0}
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{4}8'hfffx{0}
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{4}12'hfx{0}
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{4}64'o0{0}
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{4}0x7f{0}
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{4}0o23{0}
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{4}0b1011{0}
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{4}42_839{0}
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{4}0.1{0}
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{4}1.3u{0}
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{4}5.46K{0}
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{4}1.2E12{0}
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{4}1.30e{10}-{4}2{0}
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{4}236.123_763e{10}-{4}12{0}
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{2}// SCE_V_WORD {5}
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{5}always{0}
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{2}// SCE_V_STRING {6}
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{6}"\tsome\ttext\r\n"{0}
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{2}// SCE_V_WORD2 {7}
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{7}special{0}
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{2}// SCE_V_WORD3 {8}
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{8}$async$and$array{0}
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{2}// SCE_V_PREPROCESSOR {9}
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{9}`define{0} {11}__VAMS_ENABLE__{0}
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{9}`ifdef{0} {11}__VAMS_ENABLE__{0}
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{5}parameter{0} {5}integer{0} {11}del{0} {10}={0} {4}1{0} {11}from{0} {10}[{4}1{10}:{4}100{10}];{0}
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{9}`else{64}
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{69}parameter{64} {75}del{64} {74}={64} {68}1{74};{64}
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{9}`endif{0}
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{2}// SCE_V_OPERATOR {10}
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{10}+-/=!@#%^&*()[]{}<|>~{0}
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{2}// SCE_V_IDENTIFIER {11}
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{11}q{0}
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{11}x$z{0}
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{11}\my_var{0}
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{11}\/x1/n1{0}
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{11}\\x1\n1{0}
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{11}\{a,b}{0}
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{11}\V(p,n){0}
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{2}// SCE_V_STRINGEOL {12}
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{12}"\n
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{0}
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{2}// SCE_V_USER {19}
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{19}my_var{0}
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{2}// SCE_V_COMMENT_WORD {20}
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// {20}TODO{2} write a comment
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{0}
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{5}module{0} {11}mod{10}({11}clk{10},{0} {11}q{10},{0} {11}reset{10}){0} {2}// folded when fold.verilog.flags=1
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// SCE_V_INPUT {21}
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{0} {21}input{0} {21}clk{10};{0}
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{2}// SCE_V_OUTPUT {22}
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{0} {22}output{0} {22}q{10};{0}
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{2}// SCE_V_INOUT {23}
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{0} {23}inout{0} {23}reset{10};{0}
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{5}endmodule{0}
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{2}// SCE_V_PORT_CONNECT {24}
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{11}mod{0} {11}m1{10}({0}
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{10}.{24}clk{10}({11}clk{10}),{0}
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{10}.{24}q{10}({11}q{10}),{0}
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{10}.{24}reset{10}({11}reset{10}){0}
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{10});{0}
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62
3rdparty/lexilla540/lexilla/test/examples/verilog/SciTE.properties
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62
3rdparty/lexilla540/lexilla/test/examples/verilog/SciTE.properties
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lexer.*.vh=verilog
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keywords.*.vh= \
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always and assign automatic \
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begin buf bufif0 bufif1 \
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case casex casez cell cmos config \
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deassign default defparam design disable \
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edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
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for force forever fork function \
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generate genvar \
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highz0 highz1 \
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if ifnone incdir include initial inout input instance integer \
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join \
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large liblist library localparam \
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macromodule medium module \
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nand negedge nmos nor noshowcancelled not notif0 notif1 \
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or output \
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parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
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rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
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scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
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table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
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unsigned use uwire \
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vectored \
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wait wand weak0 weak1 while wire wor \
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xnor xor
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keywords2.*.vh=special
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keywords3.*.vh= \
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$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
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$bitstoreal \
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$countdrivers \
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$display $displayb $displayh $displayo \
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$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
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$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
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$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $feof $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
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$getpattern \
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$history $hold \
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$incsave $input $itor \
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$key \
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$list $log \
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$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
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$nochange $nokey $nolog \
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$period $printtimescale \
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$q_add $q_exam $q_full $q_initialize $q_remove \
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$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
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$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
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$test$plusargs $time $timeformat $timeskew \
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$ungetc $unsigned \
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$value$plusargs \
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$width $writeb $writeh $write $writeo
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keywords4.*.vh=my_var
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keywords5.*.vh=synopsys parallel_case infer_mux TODO
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fold=1
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fold.compact=0
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fold.comment=1
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fold.preprocessor=1
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fold.at.else=1
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fold.verilog.flags=1 # fold module definitions
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lexer.verilog.track.preprocessor=1
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lexer.verilog.update.preprocessor=1
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lexer.verilog.portstyling=1
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lexer.verilog.fold.preprocessor.else=1
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