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fix build under newer KConfig by bump cmake min version

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This commit is contained in:
Gary Wang
2024-09-04 19:01:58 +08:00
parent 727a2ec214
commit 9fb3681e3a
1022 changed files with 4414 additions and 1375 deletions
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3
3rdparty/lexilla540/lexilla/test/examples/vhdl/SciTE.properties vendored Normal file
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lexer.*.vhd=vhdl
fold=1

57
3rdparty/lexilla540/lexilla/test/examples/vhdl/x.vhd vendored Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity x is
port(
rst : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic_vector;
a, b : in std_logic;
v : out std_logic
);
end x;
architecture behavioral of x is
signal q_i : std_logic_vector(q'range);
begin
v <= a when b = '1' else '0';
gen: for j in q'low to q'high generate
gen_first: if j = q'low generate
variable foo : boolean := false;
begin
stage1: process (rst, clk) begin
if rst = '1' then
q_i(j) <= '0';
elsif rising_edge(clk) then
q_i(j) <= d;
case a is
when 1 =>
when 2 =>
when others =>
end case;
end if;
end process;
else generate
stages: process (rst, clk)
begin
if rst = '1' then
q_i(j) <= '0';
elsif rising_edge(clk) then
for u in 0 to 7 loop
q_i(j) <= q_i(j - 1);
end loop;
end if;
end process;
end generate;
end generate;
L: case expression generate
when choice1 =>
when choice2 =>
end generate L;
end behavioral;

58
3rdparty/lexilla540/lexilla/test/examples/vhdl/x.vhd.folded vendored Normal file
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0 400 400 library ieee;
0 400 400 use ieee.std_logic_1164.all;
0 400 400 use ieee.std_logic_arith.all;
1 400 400
2 400 401 + entity x is
2 401 402 + port(
0 402 402 | rst : in std_logic;
0 402 402 | clk : in std_logic;
0 402 402 | d : in std_logic;
0 402 402 | q : out std_logic_vector;
0 402 402 | a, b : in std_logic;
0 402 402 | v : out std_logic
0 402 401 | );
0 401 400 | end x;
1 400 400
2 400 401 + architecture behavioral of x is
0 401 401 | signal q_i : std_logic_vector(q'range);
2 400 401 + begin
1 401 401 |
0 401 401 | v <= a when b = '1' else '0';
1 401 401 |
2 401 402 + gen: for j in q'low to q'high generate
2 402 403 + gen_first: if j = q'low generate
0 403 403 | variable foo : boolean := false;
2 402 403 + begin
2 403 404 + stage1: process (rst, clk) begin
2 404 405 + if rst = '1' then
0 405 405 | q_i(j) <= '0';
2 404 405 + elsif rising_edge(clk) then
0 405 405 | q_i(j) <= d;
2 405 406 + case a is
0 406 406 | when 1 =>
0 406 406 | when 2 =>
0 406 406 | when others =>
0 406 405 | end case;
0 405 404 | end if;
0 404 403 | end process;
2 402 403 + else generate
2 403 404 + stages: process (rst, clk)
0 404 404 | begin
2 404 405 + if rst = '1' then
0 405 405 | q_i(j) <= '0';
2 404 405 + elsif rising_edge(clk) then
2 405 406 + for u in 0 to 7 loop
0 406 406 | q_i(j) <= q_i(j - 1);
0 406 405 | end loop;
0 405 404 | end if;
0 404 403 | end process;
0 403 402 | end generate;
0 402 401 | end generate;
1 401 401 |
2 401 402 + L: case expression generate
0 402 402 | when choice1 =>
0 402 402 | when choice2 =>
0 402 401 | end generate L;
1 401 401 |
0 401 400 | end behavioral;
0 400 0

57
3rdparty/lexilla540/lexilla/test/examples/vhdl/x.vhd.styled vendored Normal file
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{6}library{0} {6}ieee{5};{0}
{6}use{0} {6}ieee{5}.{6}std_logic_1164{5}.{6}all{5};{0}
{6}use{0} {6}ieee{5}.{6}std_logic_arith{5}.{6}all{5};{0}
{6}entity{0} {6}x{0} {6}is{0}
{6}port{5}({0}
{6}rst{0} {5}:{0} {6}in{0} {6}std_logic{5};{0}
{6}clk{0} {5}:{0} {6}in{0} {6}std_logic{5};{0}
{6}d{0} {5}:{0} {6}in{0} {6}std_logic{5};{0}
{6}q{0} {5}:{0} {6}out{0} {6}std_logic_vector{5};{0}
{6}a{5},{0} {6}b{0} {5}:{0} {6}in{0} {6}std_logic{5};{0}
{6}v{0} {5}:{0} {6}out{0} {6}std_logic{0}
{5});{0}
{6}end{0} {6}x{5};{0}
{6}architecture{0} {6}behavioral{0} {6}of{0} {6}x{0} {6}is{0}
{6}signal{0} {6}q_i{0} {5}:{0} {6}std_logic_vector{5}({6}q{0}'{6}range{5});{0}
{6}begin{0}
{6}v{0} {5}<={0} {6}a{0} {6}when{0} {6}b{0} {5}={0} {4}'1'{0} {6}else{0} {4}'0'{5};{0}
{6}gen{5}:{0} {6}for{0} {6}j{0} {6}in{0} {6}q{0}'{6}low{0} {6}to{0} {6}q{0}'{6}high{0} {6}generate{0}
{6}gen_first{5}:{0} {6}if{0} {6}j{0} {5}={0} {6}q{0}'{6}low{0} {6}generate{0}
{6}variable{0} {6}foo{0} {5}:{0} {6}boolean{0} {5}:={0} {6}false{5};{0}
{6}begin{0}
{6}stage1{5}:{0} {6}process{0} {5}({6}rst{5},{0} {6}clk{5}){0} {6}begin{0}
{6}if{0} {6}rst{0} {5}={0} {4}'1'{0} {6}then{0}
{6}q_i{5}({6}j{5}){0} {5}<={0} {4}'0'{5};{0}
{6}elsif{0} {6}rising_edge{5}({6}clk{5}){0} {6}then{0}
{6}q_i{5}({6}j{5}){0} {5}<={0} {6}d{5};{0}
{6}case{0} {6}a{0} {6}is{0}
{6}when{0} {3}1{0} {5}=>{0}
{6}when{0} {3}2{0} {5}=>{0}
{6}when{0} {6}others{0} {5}=>{0}
{6}end{0} {6}case{5};{0}
{6}end{0} {6}if{5};{0}
{6}end{0} {6}process{5};{0}
{6}else{0} {6}generate{0}
{6}stages{5}:{0} {6}process{0} {5}({6}rst{5},{0} {6}clk{5}){0}
{6}begin{0}
{6}if{0} {6}rst{0} {5}={0} {4}'1'{0} {6}then{0}
{6}q_i{5}({6}j{5}){0} {5}<={0} {4}'0'{5};{0}
{6}elsif{0} {6}rising_edge{5}({6}clk{5}){0} {6}then{0}
{6}for{0} {6}u{0} {6}in{0} {3}0{0} {6}to{0} {3}7{0} {6}loop{0}
{6}q_i{5}({6}j{5}){0} {5}<={0} {6}q_i{5}({6}j{0} {5}-{0} {3}1{5});{0}
{6}end{0} {6}loop{5};{0}
{6}end{0} {6}if{5};{0}
{6}end{0} {6}process{5};{0}
{6}end{0} {6}generate{5};{0}
{6}end{0} {6}generate{5};{0}
{6}L{5}:{0} {6}case{0} {6}expression{0} {6}generate{0}
{6}when{0} {6}choice1{0} {5}=>{0}
{6}when{0} {6}choice2{0} {5}=>{0}
{6}end{0} {6}generate{0} {6}L{5};{0}
{6}end{0} {6}behavioral{5};{0}