718c41634f
1.项目后端整体迁移至PaddleOCR-NCNN算法，已通过基本的兼容性测试 2.工程改为使用CMake组织，后续为了更好地兼容第三方库，不再提供QMake工程 3.重整权利声明文件，重整代码工程，确保最小化侵权风险 Log: 切换后端至PaddleOCR-NCNN，切换工程为CMake Change-Id: I4d5d2c5d37505a4a24b389b1a4c5d12f17bfa38c
86 lines
2.7 KiB
Markdown
86 lines
2.7 KiB
Markdown
## natural assembly
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* no register dependency, no penalty
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```
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ld1 {v0.4s}, [r0], #16
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fmla v10.4s, v16.4s, v24.s[0]
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fmla v11.4s, v16.4s, v24.s[1]
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fmla v12.4s, v16.4s, v24.s[2]
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fmla v13.4s, v16.4s, v24.s[3]
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```
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## A53
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* 128bit vector load cannot be dual issued with fmla, wait 2 cycles
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* 64bit vector load cannot be dual issued with fmla, wait 1 cycle
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* 64bit integer load can be dual issued with fmla, no penalty
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* pointer update can be dual issued with fmla, no penalty
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* 64bit vector load and 64bit vector insert can be dual issued, no penalty
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* any vector load cannot be issued on the 4th cycle of each fmla (enters the accumulator pipeline)
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### practical guide
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* use 64bit vector load only
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* issue vector load every three fmla
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* 1 cycle to load 64bit, dual issue with the previous interleaved 64bit insert
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* load the remaining 64bit into integer register, dual issue with fmla
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* update pointer, dual issue with fmla
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* insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load
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* add nop every three fmla if no load, seems to be faster
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```
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ldr d0, [r0] // 1 cycle, v0 first 64bit
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fmla
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ldr x23, [r0, #8] // 0 cycle, v0 second 64bit to temp register
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fmla
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add r0, r0, #16 // 0 cycle, update pointer
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fmla
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ldr d1, [r0] // 1 cycle, v1 first 64bit
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ins v0.d[1], x23 // 0 cycle, v0 second 64bit complete
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fmla
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ldr x23, [r0, #8] // 0 cycle, v1 second 64bit to temp register
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fmla
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add r0, r0, #16 // 0 cycle, update pointer
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fmla
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ins v1.d[1], x23 // 1 cycle, v1 second 64bit complete
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nop
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fmla
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fmla
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fmla
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nop
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nop
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fmla
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fmla
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fmla
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```
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## A55
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* 128bit vector load cannot be dual issued with fmla, wait 2 cycles
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* 64bit vector load can be dual issued with fmla, no penalty
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* 64bit integer load can be dual issued with fmla, no penalty
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* pointer update can be dual issued with fmla, no penalty
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* 64bit vector insert can be dual issued with fmla, no penalty
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### practical guide
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* use 64bit vector load only
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* load 64bit, dual issue with fmla
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* load the remaining 64bit into integer register, dual issue with fmla
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* update pointer, dual issue with fmla
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* insert 64bit into vector from integer register, dual issue with fmla
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* interleaved load loose register dependency
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* nop trick is not needed
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```
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ldr d0, [r0] // 0 cycle, v0 first 64bit
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fmla
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ldr x23, [r0, #8] // 0 cycle, v0 second 64bit to temp register
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fmla
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add r0, r0, #16 // 0 cycle, update pointer
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fmla
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ldr d1, [r0] // 0 cycle, v1 first 64bit
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fmla
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ins v0.d[1], x23 // 0 cycle, v0 second 64bit complete
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fmla
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ldr x23, [r0, #8] // 0 cycle, v1 second 64bit to temp register
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fmla
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add r0, r0, #16 // 0 cycle, update pointer
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fmla
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ins v1.d[1], x23 // 0 cycle, v1 second 64bit complete
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fmla
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```
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